14-bit 125MSPS quad ADC for enhanced SNR performance with back-end digital summing

Q3307LC41105900 14

Circuit function and advantage

The circuit shown in Figure 1 is a simplified diagram of a 14-bit, 125 MSPS four-channel ADC system that uses a back-end digital summation to boost the signal-to-noise ratio (SNR) from 74 dBFS for a single-channel ADC to 78.5 dBFS for a four-channel ADC. This technology is ideal for applications that require high SNR (such as ultrasound and radar) and utilizes modern high performance, low power, quad pipelined ADCs.

This circuit uses the basic principle that the uncorrelated noise sources are added on a square and root (rss) basis, and the signal voltages are added on a linear basis.

Figure 1. Basic block diagram of four parallel ADC summations for higher SNR