Based on CC4024 counter constitutes optional frequency division coefficient delay circuit

The CC4024 is a 7-bit binary serial counter. All counters are live from the trigger. The counter counts on the falling edge of the clock. When the CR bit is high, the counter is cleared, since the teardown trigger is used at the clock input. There is no limit to the pulse rise and fall times, and all inputs and outputs are buffered.
The delay circuit with optional frequency division coefficient is composed of two 7-bit binary serial counters CC4024, a controllable pulse source (composed of gates 1, 2), and input and output control circuits.