Foreword
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As the speed of the car increases, the road traffic density increases, and the requirements for the safety performance of the car are also higher and higher. The car's anti-lock braking system (ABS) came into being. It is a mechatronic system based on the traditional braking system, using electronic control technology to prevent wheel lock during braking.
Anti-lock system based on dual CPU structure
The following problems are mainly considered in the design of ABS system: Firstly, because the ABS system directly relates to the safety performance of the vehicle, its fault problem is extremely important. The system must ensure that the fault can be detected in time and the fault point is accurately determined. Secondly, the ABS system usually Inductive loads such as solenoid valves are included, the drive current is large, and appropriate drive circuits are required. In addition, in order to facilitate communication between the ABS system and other systems on the vehicle, the system needs to reserve a communication interface.
Based on the original four-sensor four-channel (4S/4M) ABS electronic control unit, this paper developed a pneumatic ABS with an applause self-test. The dual CPU structure of MCU+CPLD is adopted in the design. The system structure is shown in Figure 1 (figure, please refer to “Electronic Design Application†2005.8).
The control CPU collects the wheel speed signal, and then performs road surface recognition and brake control according to the set deceleration and slip rate thresholds. It is also responsible for static detection of the wheel speed sensor. The safety CPU (CPLD) is mainly responsible for the fault detection of the ABS system, determines the fault location, and transmits the corresponding fault code to the control CPU. After the fault occurs, the control CPU uniformly processes the fault state, including interrupting the ABS function, returning to the normal brake, lighting the fault display light, and storing the corresponding fault code in the EEPROM, and randomly passing through the CAN communication port when needed. Transfer to the host computer or other electronic control system on the vehicle.
System hardware design
The faults of the ABS system are mainly the failure of the solenoid valve, the failure of the wheel speed signal acquisition system, the failure of the brake line pressure signal acquisition system, the power failure and the controller failure. The system gives corresponding diagnostic circuits for these faults.
Overview of MC9S12DP256B and CPLD
The MC9S12DP256B is a high speed, high performance 5.0V FLASH microcontroller based on a 16-bit HCS12 CPU and 0.25um manufacturing process. The MCU uses phase-locked loop technology or internal frequency multiplication technology to make the internal bus speed much higher than the clock generator. The clock frequency used at the same speed is much lower than that of similar MCUs, so the high-frequency noise is low and anti-interference. Strong ability, more suitable for the harsh environment inside the car. It also includes timers, A/D conversion, PWM output, CAN communication, EEPROM, SPI, SCI and other modules. It is rich in resources and meets the development requirements of system functions.
The CPLD in the system uses the XC9572TQ100, which supports extended industrial temperature ranges. It not only has a wider operating temperature range, from -40C to +100C, but it also meets the automotive industry's unique quality certification standards. In addition, the number of gates and the number of I/Os of the chip meet the design requirements, leaving room for functional expansion.
Digital input channel diagnostic circuit
Whether the wheel speed input signal is correct or not directly affects the work of the ABS system. To this end, a digital switch is specially added before the signal processing circuit to facilitate the system to detect the digital input channel of the circuit board. Using the input simulation method, a set of standard square wave signals are sent from the safety CPU (CPLD) to the digital channel to the input capture port of the control CPU for measurement. The specific circuit is shown in Figure 2 (figure, please refer to "Electronic Design Application" 2005.8).
The CPLD generates a DETECT signal to control the on/off of the digital switch CD4066. When the ABS is powered on, the DETECT is “0â€, the switch is opened, and the wheel speed signal is shielded. At this time, the standard square wave defined by the CPLD is generated (the frequency is 100 Hz, that is, each counting period (0.1 s) 10 Pulses) and output to the main CPU. The main CPU captures the square wave through the ECT port for measurement and calculation. After comparing with the defined frequency of the standard wave, if the result is consistent, the digital input channel is normal, otherwise it indicates that a fault has occurred. After the detection is completed, after everything is normal, DETECT becomes "1", the switch is turned on, and the wheel speed signal is output to the control CPU through the signal shaping amplification unit and by the CPLD.
Solenoid valve drive and fault detection circuit
The operating current of the solenoid valve in the automotive brake system is 1.5-2.5A, and the output current of the microcontroller is far below this requirement. Therefore, the high-end driver chip MC33289 of Freescale is used to drive the solenoid valve. The single-channel control circuit is shown in Figure 3 (figure, see Electronic Design Application, Version 2005.8).
Due to the self-test function of the MC33289, the ST pin can be directly connected to the CPU during application. Once the solenoid valve fails, such as short circuit or open circuit, the ST is automatically deactivated. The CPU stops the ABS function immediately after receiving the signal, and the fault display is illuminated. The lamp, at the same time, transmits the corresponding fault code to the control CPU in the form of an interrupt. The detection of the solenoid valve drive condition is accomplished by comparing the output OUT of the MC33289 with the input IN. Under normal circumstances, the two logic values ​​of the same road should be equal, and it is "1" or "0". If they are not equal, the driver chip is faulty. The CPU must interrupt the ABS function, illuminate the fault display light and transmit the fault code. .
Fault code storage and transmission
The MC9S12DP256B comes with 4KB of EEPROM with addresses from 0x400 to 0xFFF. No need to expand the EEPROM, it can be used to store the fault code, and it is convenient for long-term data storage.
Before the erase and write operations, the module clock must be configured between 150KHz and 200KHz by setting the EEPROM clock distribution register ECLKDIV. The crystal oscillator in the system is 16MHz, the bus frequency is 8MHz. After calculation, ECLKDIV=0x4A is taken, that is, the prescaler factor PRDIV8=1, the frequency dividing factor EDIV[5:0]=001010, and the module clock is 182KHz.
Since each write operation is performed in words, for security reasons, two words are erased each time the erase is performed. The timing of the erase operation is exactly the same as the write operation, except that the data written to the corresponding address is "0".
In addition, the system combines its own CAN module, selects the PCA82C250 of Philips, and sets the interface circuit of CAN to facilitate the transmission of fault codes. The interface circuit is shown in Figure 4 (figure, please refer to "Electronic Design Application" 2005.8).
Other circuits in the system, such as the wheel speed signal processing circuit, the sensor static detection circuit, the power supply monitoring circuit, etc., are limited by the length and will not be described in detail here.
System software and VHDL language design
The system's control CPU MC9S12DP256B is developed in C and assembly language, while CPLD is programmed in VHDL language.
The functions of the MC9S12DP256B program are: self-test of program memory and data memory; static and dynamic detection of wheel speed sensor; acquisition of wheel speed signal, calculation of wheel speed and deceleration, output of brake pressure adjustment signal according to control logic; real-time storage Fault code; CAN communication.
The functions of the CPLD program are: controlling the on/off of the digital switch CD4066; detecting the digital input channel; monitoring the working state of the solenoid valve driving chip and the solenoid valve; and transmitting the fault condition to the control CPU. The CPLD design consists of four steps: design input, implementation, verification, and chip programming. The design uses VHDL language text input, which is integrated, simulated, and implemented, and then downloaded to the Xilinx chip through the parallel cable. Figure 5 and Figure 6 (figure, please refer to "Electronic Design Application" 2005.8) are the flow chart of the system control CPU and CPLD.
Conclusion
With its unique dual CPU structure, the system integrates anti-lock braking and system fault detection, and can realize the transmission of fault detection code. At the same time, both CPUs reserve a certain input/output port, which provides a possibility to further expand the functions of the electronic control unit of the car.
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