Although 74LS573 and 74HC573 are both 8-D latches (three-state), and they are exactly the same in logic, their pin definitions are different. 74LS373 is a TTL circuit, and the power supply voltage is 5V. The pull-up is weak and the pull-down is strong. There is a pull-up inside the input, and it is high when the input is open. 74HC573 is a CMOS circuit with a power supply voltage operating range of 2V ~ 6V. The pull-up and pull-down capabilities are the same. The input resistance is very high, and the level is uncertain when the input is open. There are still many differences between 74LS573 and 74HC573, whether in terms of their pin diagrams, parameters, or applications. Although there are many differences, they are the same on a certain level. This article mainly compares the similarities and differences between 74LS573 and 74HC573, explains in detail their working characteristics and performance parameters, and compares which is more suitable for driving the common cathode digital tube.
74ls37374LS373 is a commonly used address latch chip, composed of eight parallel D flip-flops with three-state buffered output. In order to expand the external memory in the one-chip computer system, usually need a 74LS373 chip. This article will introduce the working principle of 74LS373, which covers pin diagrams, internal structure, main parameters and typical application circuits in the microcontroller expansion system.
74HC573 contains eight-way 3-state output non-inverting transparent latch, is a high-performance silicon gate CMOS device. SL74HC573 has the same pins as LS/AL573. The input of the device is compatible with standard CMOS output, and with pull-up resistors they can be compatible with LS/ALSTTL output.
74ls373 working principle
(1). Pin 1 is the output enable (OE), which is active at low level. When pin 1 is at high level, no matter what input 3, 4, 7, 8, 13, 14, 17, 18 or 11 is How about the pin (latch control terminal, G), output 2 (Q0), 5 (Q1), 6 (Q2), 9 (Q3), 12 (Q4), 15 (Q5), 16 (Q6), 19 (Q7) ) All are in a high-impedance state (or floating state);
(2). When pin 1 is low level, as long as there is a falling edge on pin 11 (latching control terminal, G), output 2 (Q0), 5 (Q1), 6 (Q2), 9 (Q3), 12 (Q4) , 15 (Q5), 16 (Q6), 19 (Q7) immediately present the status of input pins 3, 4, 7, 8, 13, 14, 17, 18.
When the latched terminal LE changes from high to low, the 8-bit information at the output terminal is latched until the LE terminal becomes valid again. When the tri-state gate enable signal OE is low, the tri-state gate is turned on and allows Q0~Q7 to be output. When OE is high, the output is suspended. When 74LS373 is used as an address latch, OE should be set to low level. At this time, when the latch enable terminal C is high, the output Q0~Q7 state is the same as the input terminal D1~D7 state; when C is negative During the transition, the data at the input terminals D0~D7 are locked into Q0~Q7. The ALE signal of 51 single-chip microcomputer can be directly connected with C of 74LS373. 74ls373 and MCU interface:
1D~8D are 8 input terminals. 1Q~8Q are 8 output terminals.
G is the data latch control terminal; when G=1, the latch output terminal is the same as the input terminal; when G changes from "1" to "0", data is input into the latch.
OE is the output enable terminal; when OE="0", the three-state gate is open; when OE="1", the three-state gate is closed, and the output is in a high-impedance state.
In the MCS-51 single-chip microcomputer system, 74LS373 is often used as an address latch, and its connection method is shown in the figure above. The input terminal 1D~8D is connected to the P0 port of the single-chip microcomputer, the output terminal provides the low 8-bit address, and the G terminal is connected to the address latch enable signal ALE of the single-chip microcomputer. The output enable terminal OE is grounded, indicating that the output tri-state gate is always open.
74ls373 truth table
74HC573 working principle
The eight latches of 74HC573 are all transparent D-type latches. When the enable (G) is high, the Q output will change with the data (D) input. When the enable is low, the output will be latched on the established data level. The output control does not affect the internal work of the latch, that is, the old data can be retained, even when the output is turned off,
74HC573 truth table
The difference between 74LS373 and 74HC573 working parameters and working conditions
74LS373 working parameters
74ls373 working conditions
74hc573 parameters
74hc573 working conditions
The different functions of 74LS373 and 74HC573 in the application circuitFor example, the application circuit of 74LS373 in the SCM expansion system
When 74LS373 is used as an address latch, OE should be set to low level. At this time, when the latch enable terminal G is high, the state of output Q0-Q7 is the same as that of input terminals D1-D7; when G is negative During the transition, the data at the input terminals D0-D7 are locked into Q0-Q7. The ALE signal of the 51 single-chip microcomputer can be directly connected to the G of the 74LS373. In the MCS-51 microcontroller system, the connection method is shown in the figure below. The input terminals 1D-8D are connected to the P0 port of the single-chip microcomputer, the output terminal provides the low 8-bit address, and the G terminal is connected to the address latch enable signal ALE of the single-chip microcomputer. The output enable terminal OE is grounded, which means that the three-state output gate is always on and can send out address signals.
1D-8D are 8 input terminals. 1Q-8Q has 8 output terminals.
74HC573 simple application
Two 74HC573 latches are connected to the P3 port at the same time, the output enable terminals OE of the two chips are both grounded, the data latch enable terminal LE is connected to P2^6 and P2^7 respectively, and the output data terminal Qn of the latch Both are connected to the LED bar display. In this example, the upper four LED lights of U4 are lit by assigning different values ​​to the P3 port, and the lower four LED lights of U5 are lit.
Similarities between 74LS373 and 74HC573 One: High resistance state
That is, the output is neither high level nor low level, but high impedance state; in this state, multiple chips can be output in parallel; however, only one of these chips can be in a non-high impedance state. Otherwise, the chip will be burned, and the concept of high impedance state can also be used in RS232 and RS422 communication.
Two: data latch
When the input data disappears, the data remains at the output end of the chip; this concept is often used in parallel data expansion.
Three: data buffer
Strengthen the driving ability. Both 74LS373/74LS573 have data buffering capabilities.
Which 74LS373 or 74HC573 is more suitable for driving common cathode digital tubes?To compare the common cathode connection method, 74HC573 is suitable. Because the 74HC573 drive current is large, the current can flow out at high level of 20MA. The current flow out of 74LS373 at high level is 2.6MA. So 74HC573 is suitable.
to sum upAlthough 74LS573 and 74HC573 are eight D latches, 74LS is a TTL type integrated circuit, and 74HC is a CMOS integrated circuit. LS and HC have different definitions of high level and low level. HC high level is specified as 0.7 times the power supply voltage, and low level is specified as 0.3 times the power supply voltage. LS stipulates that the high level is 2.0V and the low level is 0.8V. Different load characteristics. HC has the same pull-up and pull-down capabilities, LS has weak pull-up and strong pull-down. The input characteristics are different. The HC input resistance is very high, and the level is uncertain when the input is open. The LS input has an internal pull-up, and it is high when the input is open.
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