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Abstract: This paper designs an MPEG4-based video compression coding card for industrial control applications. After supporting 4 channels of analog video image acquisition and A/D conversion, the code card and the host communicate with the host according to the PCI2.2 standard. The overall design of the encoder card is described in detail. The system uses the latest MPEG4 compression method for encoding, which provides optimized hardware design for the entire digital monitoring system and video network transmission system.
Keywords: PCI acquisition coding MPEG-4 industrial control
1 Introduction
With the rapid development of communication network technology, people's concept has also followed the pace of the times, and has integrated itself into the network age. For example, viewing information, monitoring, communication, etc. all use the network. Although the network has brought us a lot of information flow, with the accelerated pace of people's life, the transmission rate requirements are getting higher and higher, especially when transmitting in real time. By using MPEG4 video and audio codec technology, satellite Internet broadcast technology solves this problem, making digital video broadcast image resolution up to 192 × 144 × 25FPS (PAL) / 384 × 288 × 25FPS (PAL), image and screen transmission Through the satellite channel, the average code traffic is less than 384K; the text message data, the external interaction through the Web to the public network, the average code traffic is less than 56K, realizing point-to-point, multi-point instant broadcast and synchronous interaction, won the praise of the majority of users. It provides an efficient, intuitive, relevant and practical tool for enterprises, government agencies, organizations, and network hospitals and online schools, as well as personal visual communication.
Digital video signals have incomparable advantages over analog video signals. Digital coding compression of video signals comes at a price, and the cost of compression determines the cost of the system. Digital video surveillance has only entered the practical stage after the emergence of a single video encoding chip. In order to meet the diverse requirements of digital video surveillance applications, video processors using SOC technology (VIDEO PROCESSOR, some also called DSP) will dominate the mainstream of digital video surveillance products. In surveillance applications, video image digitization is real-time encoded and compressed, which is completely different from VCD and DVD programming (VCD and DVD programming can take dozens or even hundreds of times to encode and compress). Due to the great advantages of MPEG4, it provides a new technical approach for implementing security inspection and security prevention using image measurement and control and image processing. The characteristics of the digital video surveillance video system: the playback image quality is good, never distortion; the video file retrieval is convenient, easy to check management, remote transmission or further image processing, improve the availability of image data; multi-screen processing function, video recording function Integrated with control functions, low equipment, high reliability and easy maintenance.
2 overall framework of the system
Vweb's Vweb2010 supports the form of PCI interface card. The system program is stored in the hard disk or memory of the motherboard, and the program is loaded into the system through the interaction between the motherboard and the system. This approach is very flexible and works well with other systems. The code card designed in this paper is WDM driven under Windows system and exists in the form of PCI interface card. The block diagram of software and hardware is shown in Figure 1.
Figure 1 System block diagram
The code card is inserted in the PCI slot and processes the video signal based on the Windows system. The whole system is connected to the motherboard through the PCI bus. In the application, the motherboard provides program storage space for the entire code card, and is responsible for program loading and some initialization work. When the initialization and the loading of the program are finished, the relationship between the motherboard and the encoding card is the storage and transmission of MPEG4 data, communication with the application, etc., and the encoding board can separately perform the multimedia data processing work to be performed. In more cases, the motherboard always keeps in contact with the code card through the PCI bus, which can coordinate the work of the motherboard and the code card, and also facilitate the exchange of data between the motherboard and the code card.
The Vweb2010 chip provides a multimedia interface module, which is used in this design with a PCI interface, a video input unit, and an audio input unit. The PCI interface is connected to the PCI on the motherboard through the PCI bridge; the other units are connected to the A/D modules on the code board, and around these interface units, we can design a frame between the modules of the code card.
When the system starts, the MPEG4 compression chip reads the startup code of the startup circuit, activates the corresponding download program to download and run the microcode from the corresponding port, and the other chips complete the initialization through the I 2 C bus, and the system starts the MPEG4 codec process. After the analog video is A/D converted by SAA7114H, the real-time video stream is sent from the VPO port to the VPO port of the encoding part of the MPEG4 compression chip, and the analog audio is converted from the MPEG4 compression chip by the A/D conversion of the PCM1801U. I 2 S input. The MPEG4 compression chip is connected to the bridge chip through the PCI interface, and the encoded compressed data is bridged by the bridge chip and transmitted to the PCI bus for remote transmission or local storage.
3 MPEG4 encoding module design in hardware
The PCI encoding card is functionally divided into three modules. The first is the front-end A/D conversion module, which consists of two major blocks of video and audio processing. This paper uses SAA7114H video A/D chip to provide analog video to digital video (ITU-R.BT.656 format) conversion, and PCM1801U for audio. A/D sampling is connected to the MPEG4 codec chip through I 2 C. This is followed by the MPEG4 encoding compression module. It consists of MPEG4 codec chip and its peripheral circuits, mainly to complete the compression function of real-time video and audio data. Finally, the bridge chip driver module uses the zero-reaction time PCI-PCI bridge product HB1, which supports the PCI2.2 specification and supports 32-bit 33MHz PCI operation. Through the chip, the bridging function can be realized, and multi-chipset support can be realized.
3.1 video and audio processing module
In the video A/D conversion module, PHILIPS' SAA7114H is used. This is a video A/D sampling chip, which mainly has the following functions and features:
The chip has six inputs that can simultaneously support six CVBS (composite video signals), or two Y/C (luminance and chrominance separated signals, generally referred to as S-terminal) signals and two CVBS signals, or It is a Y/C signal and four CVBS signals. The user has programmable control, selects the input channel, and the static gain and automatic gain of each signal. It has two sets of analog image anti-aliasing filter and two sets of A/D conversion circuits embedded in it; automatic detection of 50Hz and 60Hz field frequency and PAL and NTSC images, supporting all types of TV Signal input; I 2 C bus interface rate up to 400kb / s.
In this system, SAA7114H supports the ITU-R.BT.656 format, and uses the ITU-R.BT.656 standard to embed row and field synchronization information in the data to provide row and field information. At the same time, for the convenience of hardware implementation, a composite video (CVBS) input port (AI24, Pin10 leg) is fixed. Of course, these require an I 2 C bus to configure. The connection of the I 2 C bus control pin is connected by U14 and Y17 of Vweb2010, where U14 is connected to the clock line and Y17 is connected to the data line. The SAA7114H supports a power-saving mode. The power is less than 0.5W during operation. It requires 3.3V power supply and the I/O port withstand voltage is 5V. This power supply is provided by the PCI bus. The method used to prevent input overvoltage and overcurrent is to place a composite Schottky diode on the input port. Analog and digital power supplies, analog ground and digital connections are connected by magnetic beads. The SAA7114H has multiple internal registers for setting its operating state. Two I 2 C bus pins, SDA (32 pins) and SCL (31 pins), are externally provided for accessing internal registers. All of these registers are read and written by Vweb2010. During operation, the pins LLC, LLC2, XTOUT, RTS0, RTS1 and RTCO of the SAA7114H are set in a three-state state, and the luminance and chrominance are adaptively adjusted by the comb filter. .
3.2 MPEG-4 encoding compression module
The MPEG-4 encoding module uses a dedicated chip Vweb2010, which is a dedicated video compression chip (Video ASIC) designed by Vweb for multimedia signal processing. The chip is characterized by the compression of standard compression algorithms such as MPEG1, MPEG2, MPEG4 and H.263. Therefore, the implementation scheme has the advantages of low development cost, short development cycle, and fast calculation speed. It can perform both one-way encoding and one-way decoding. Its audio encoder receives dual-channel I 2 C standard digital audio signals and compresses them using MPEG1, MPEG2, MP3, AAC and AC-3 standards. The decoder receives the BIT stream in MPEG format and decodes the digital video of the standard ITU-R.BT.656 standard. Audio decoding outputs I 2 S, S/P-DIF or IEC-61937 standard audio signals. It includes an embedded RISC/DSP processor, an encoder module, a decoder module, and a system module. Its structure is shown in Figure 2.
The 8-bit ITU-R.BT.656 video stream output by the SAA7114H is received through the video encoding input interface (VPO port) of the chip. The clock interface of the chip is connected to an external clock signal (27MHz), of which the internal clock pin (PLL_amclk_enc) It is connected to the video clock pin to ensure audio and video synchronization. The standard I 2 S audio signal is input from the PCM 1801 to the corresponding audio interface of Vweb 2010, encoded by the audio coding unit, and sent to the output unit module. SDRAM is the running space of the Vweb2010 program, and the Vweb2010 chip can support up to 128 Mbytes of SDRAM. Because Vweb2010 provides SDRAM interface, it can be directly connected to SDRAM. A 2M*32 SDRAM chip is used in this system, which is 64Mbytes in total.
3.3 PCI Bridge Module
The encoded data of the MPEG4 compression chip is bridged by the driver and arbitration of the bridge chip, which enables four MPEG4 compression chips with PCI interface to communicate with the PCI bus, supports the PCI2.2 specification, and supports 32-bit 33MHz PCI operation. . The PCI interface board has a 33MHz 32bit PCI bus conforming to the PCI specification V2.2; including address and data multiplexing AD[0:31]; control signals: PCICLK; REQ#; C/BE[0:3]; IRDY#; DEVSEL #; LOCK#; PERR#; SERR#; STOP#; TRDY#; FRAME#; IDSEL; GNT#; RST#.
Figure 2 Block diagram of Vweb2010
4 PCB design considerations
In the PCB design, wiring is an important step to complete the product design. It can be said that the previous preparation work is done for it. In the whole PCB, the wiring design process is the highest, the trick is the finest, and the workload is the largest. The PCB wiring has single-sided wiring, double-sided wiring, and multilayer wiring. There are also two ways of wiring: automatic routing and interactive wiring. Before automatic routing, you can use interactive pre-wired lines that require more stringent requirements. The edges of the input and output should avoid adjacent parallel to avoid reflection interference. If necessary, ground wire should be isolated. The wiring of two adjacent layers should be perpendicular to each other, and parasitic coupling is easy to occur in parallel.
The routing rate of automatic routing depends on a good layout, and the wiring rules can be preset, including the number of bending of the traces, the number of vias, the number of steps, and the like. Generally, the exploration wiring is first performed, the short wires are quickly connected, and then the labyrinth wiring is performed. First, the wiring to be cloth is optimized for the global routing path, and the laid wire can be disconnected as needed. And try to re-route to improve the overall effect.
In addition, the frequency of the digital circuit is high, and the sensitivity of the analog circuit is strong. For the signal line, the high-frequency signal line is as far as possible away from the sensitive analog circuit device. For the ground line, the entire PCB has only one node to the outside. Therefore, it is necessary to carry out the problem of processing the number and the common mode inside the PCB, and the digital ground and the analog ground inside the board are actually separated, and they are not connected to each other, but only at the interface where the PCB is connected with the outside world (such as a plug, etc.) ). The digital ground is slightly shorted to the analog ground. Please note that there is only one connection point. There is also no common ground on the PCB, which is determined by the system design.
5 summary
The innovation of this paper is the video acquisition and processing system in Windows, which uses MPEG4 for image compression coding, digitally processing locally and packaged for transmission to the network, so that all functions of the digital video acquisition system are integrated on this small board. It is very convenient to use. After testing, the performance of the board has reached the pre-design requirements, the work is stable, the utility is high, basically can meet the requirements of customers, and has certain competitive ability in business.
references:
1 R. Talluri, "Error-Resilient Video Coding in the ISO MPEG4 Standard", IEEE Communications Magazine, Vol. 36 No. 6, June 1998, pp. 112-119.
2 Y. Pourmohammadi, K. Asrar Haghighi, A. Kaheel, HM Alnuweiri, ST Vuong; On the Design of a QoS-aware MPEG4 Multimedia Server, IST2001
3 AM Mohamed, HM Alnuweiri, MPEG4 Broadcast: A Client/Server Framework for Multi-Service Streaming Using Push Channels, MMSP2001.
4 Huang Wei Xu Zhilong, etc., PCI bus-based data acquisition interface design, Beijing, "Microcomputer Computing Information", 2006. No. 3-1, p144
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