PCI local bus is not only the latest computer bus, but also the most compatible and most complete computer bus. It supports multiple sets of peripherals at the same time, and is independent of the processor, providing high-performance, high-throughput, low-latency data paths for CPUs and high-speed peripherals. The development of new technologies such as graphical user interface (GUI), high definition television (HDTV), and three-dimensional video multimedia display, as well as the widespread demand for high-speed communication systems, have made PCI a promising application. In response to this trend, many foreign chip manufacturers have designed and produced a variety of PCI ASICs.
At present, the PCI bus interface of domestic system manufacturers generally adopts foreign PCI special chips, such as Qspan of TUNDRA, 9050 of PLX, 21554 of INTEL, etc., but these special chips are expensive, complicated, and cannot be flexibly configured, which is not conducive to the system. Upgrade optimization, difficult to apply. To this end, major FPGA vendors have introduced PCI IP modules (soft, solid or hard) based on the structure and process of their respective programmable logic devices. The PCI cores of Xilinx, Altera, Actel and QuickLogic are widely used in China. They have their own characteristics. In general, Xilinx's PCI Core is an HDL gate-level netlist format with layout information, which is convenient for VHDL method design and Simulation verification in a third-party EDA software environment; Altera's PCI Core is in AHDL format, providing layout and wiring constraints through ACF files, with fewer user-side signals, simple functions, and easy implementation; Actel and QuickLogic's anti-melting The silk structure makes its programmable chip have certain advantages in speed and performance, but the function of the PCI core is relatively weak.
According to the actual requirements of the PCI bus interface of advanced communication systems such as VoIP and CDMA, we decided to use Altera's 64-bit 66MHz PCI Core through evaluation and comparison. On the VERIBEST and MAXPLUSII NT design platforms, we will use VHDL for the target device FLEX10K 100E. The hardware description language is designed from the PCI bus to the FPGA bridge chip of the Motorola CPU. The chip is interposed between the PCI bus and the Motorola CPU. It provides address translation, command decoding, data buffering and transmission, and plug-and-play configuration between the two buses, providing a seamless interface for high-speed data transmission.
1. Design input
Design inputs include VHDL code design and functional simulation. Before designing, the system is divided into functional modules, and the top two modules are instantiated: Altera's PCI Core and user-side logic. The user side logic is further refined according to the function. The structural features of VHDL are very convenient for hierarchical design. Each engineer is responsible for completing the design simulation of each sub-module with relatively independent functions, and finally performing the overall functional simulation. Before performing the overall function simulation, first extract the functional simulation model of PCI Core. In the MAXPLUSII environment, configure the relevant parameters of the PCI Core according to the system requirements, then compile and lay out the wiring. At this time, it is not necessary to generate an ACF file. In order to output the VHDL netlist for simulation in the VERIBEST environment, you need to select VHDL NETLIST WRITER under the INTERFACE menu during compilation. Considering that it is possible to simulate the gate-level delay after synthesis, it is best to generate the SDF standard delay file during compilation. In the INTERFACE menu, VHDL OUTPUT FILE[.VHO] (WRITE DELAY CONSTRUCTS TO column). After completing the above key settings, you can get the PCI Core VHDL netlist file with delay. Other Altera MegaCore sub-modules instantiated in the user-side logic module can be obtained by the same operation.
When the user-side logic module is interconnected with the PCI Core, there are some key issues to be aware of. The PCI Core supports the PCI master/slave mode, and the user-side master/slave mode signals are separated. When the PCI Core is in one mode of operation, the signal of the other mode must be in a certain invalid state and cannot be in a floating state or High resistance state. The three-state signal should be avoided inside the user-side logic module. For ease of control and debugging, the state machine design should be adopted. For the interaction between the PCI clock and the CPU clock, a handshake signal should be used.
Functional simulation is performed in the VERIBEST99 FPGA DESIGNVIEW environment. In the simulation, you must first configure access to the PCI Core and configure the corresponding bits in the PCI Core internal configuration register.
2. Design implementation
Design implementations include logic synthesis and place and route. After the functional simulation is completed, the next step is the synthesis of user logic. VERIBEST supports two FPGA synthesizers; FPGA EXPRESS and SYNPLIFY. FPGA EXPRESS has simple operation, clear interface and good overall efficiency, but its SCHEMATIC VIEW function is poor, and the generated schematic is difficult to understand, which is not conducive to in-depth timing analysis. SYNPLIFY provides two schematics, RTL VIEW and Technology VIEW, which facilitates the search and analysis of critical paths. It also provides many powerful attribute parameters, but it also increases the complexity of software usage.
The FPGA IP module (PCI core, dual port RAM, etc.) instantiated in the VHDL language should not participate in logic synthesis. You can add the FPGA EXPRESS integrated switch-RPAGMA SYNTHESIS_OFF or SYPLIFY integrated switch-SYNTHESIS TRANSLATE_OFF to the VHDL source code. Remove the VHDL netlist file of the FPGA IP module from the comprehensive file list.
Logic synthesis should be carried out in modules, to find out the critical path inside each sub-module, to modify the design, optimize the data path, and finally the top-level synthesis. It is best to retain the design hierarchy when synthesizing the top layer. For the associated signals between modules, since they generally go through multi-level lookup tables, causing large delays, pipeline technology should be used to add appropriate number of flip-flops to these critical paths to reduce the delay. Some settings on the software are also beneficial to improve the frequency of the integrated circuit, such as the state machine using ONE HOT encoding, reducing the number of FANOUT, shielding the operand sharing function. Through the above method, the frequency of our design integrated circuit is increased from 38MHz to 63MHz.
After the completion, it can generate EDIF files for layout and routing in MAXPLUSII environment. For gate level simulation, VHDL netlist files with delay can also be generated at the same time. After importing the EDIF file in MAX-PLUSII, set the relevant parameters under the ASSIGN menu and indicate the library path of the PCI Core. Set EDIF NETLIST READER to SYNOPSYS or SYNPLIFY when compiling EDIF files. For the first place and route, it is best not to add ACF files. After the completion, generate the ACC file of the PCI Core as required and put it in the working directory, add its own constraints, and then perform the second place and route. At this time, set the VHDL netlist file for function verification of VERIBEST. After the place and route, time parameter analysis is performed. Our design result is that the PCI clock is 30MHz and the CPU clock is 57MHz.
3. Design verification
Design verification includes static timing analysis, functional verification, and board-level verification. Static timing analysis is used to analyze whether the setup/hold time, clock-to-output time, and other time parameters meet the PCI specification. The 33MHz, 32-bit PCI specification requires a setup time of less than 7ns, a hold time of 0ns, and a clock-to-output time of less than 11ns. The analysis must take into account the effects of the trigger and perform a detailed calculation of the critical path. MAXPLUSII provides better static timing analysis. The design engineer is responsible for setting and assigning time parameters. After the software calculates, the analysis results are given. If the requirements are not met, the relevant constraints can be added when re-layout. After the timing analysis is finished, functional verification is also required. In the VERIBEST environment, the VHDL netlist generated after the place and route is simulated. At this time, OPEN POST_LAYOUT SIMULATOR should be selected to enter the emulator. VERIBEST will automatically generate a port mapping file in VHDL format and automatically associate the SDF file with no additional settings. At this time, the function simulation is relatively difficult to debug, and the relationship between signals can be queried through the VHDL netlist file.
Board-level verification of PCI Core-based FPGA design can consider the PCI Universal Development Board provided by Altera Corporation. This board supports all of Altera's PCI MegaCore modules. Users can implement user logic through SDRAM, PMC slot and RS232 port on the board. The PCI Core interface can also implement the user logic function by using the on-board PROTOTYPE area. The PCI development board demo software can display data transfer rates, as well as debug and configure PCI Core.
The PCI design based on the IP module provides an effective way for the user to implement the PCI interface on the FPGA target device. The design engineer can focus on the non-PCI part by using the IP module provided by the FPGA manufacturer with the schematic and state machine. The organic combination of design methods such as HDL language adopts a hierarchical structure to complete the design of complex electronic systems in a short time in a powerful EDA software environment.
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