With the development of communication technology, the traditional analog walkie-talkie can no longer meet people's needs, and the digitalization of walkie-talkies is imperative. The rapid development of the information society has made spectrum resources more and more valuable, and channel utilization has become a key factor. How to improve the transmission efficiency by compressing the source under limited channel resources has become one of the urgent problems to be solved. The computing power of DSP digital signal processor is getting stronger and stronger. This design uses TI's general-purpose DSPTMS320C5509A as the processor of the baseband system, mainly for the G.723.1 voice compression coding in the digital walkie-talkie baseband system with limited frequency band and DSP resources. Specific applications for research and implementation.
1G.723.1 voice compression coding principle
The G.723.1 standard is mainly used for compression of voice and other multimedia sound signals. The algorithm is part of the H.324 family of standards and includes two operating rates: low rate (5.3 kbps) using algebraic digital linear excitation prediction (ACELP), high rate (6.3 kbps) using multi-pulse excitation maximum likelihood quantization (MP_MLQ) ). Both rate encoders use frame as the processing unit, the frame length is 30ms, plus another 7.5ms delay, a total of 37.5ms algorithm delay. The principle of the encoder is shown in Figure 1.
The input 16-bit linear PC code stream is divided into speech frames of 240 samples in length. Each frame signal passes through a high-pass filter to remove low-frequency components and is divided into 4 sub-frames, 60 samples per sub-frame. A 10th order LPC prediction is performed for each subframe, and the LPC parameters of the last subframe are converted into line spectrum pair LSP parameters. Quantization is performed using predictive split vector quantization (PSVQ). In order to reduce the error of the synthesized speech signal at the synthesizing end, after the LSP coefficient is decoded and interpolated at the analysis end, it becomes an LPC coefficient. The coefficients of the formant weighting filter can be obtained from the LPC coefficients analyzed by the LPC. The formant weighted filter is used to perform the formant weighted filtering on the high-pass filtered speech signal to obtain the formant-weighted filtered speech signal f(n). The open-loop pitch period can be obtained from the f(n) pitch estimation, and the search range of the pitch period is 18 to 142 samples. The harmonic signal shaping and impact response calculation are performed on the speech signal of each sub-frame, and then the closed-loop pitch search is performed to obtain the closed-loop pitch period and the pitch gain, and then the residual signal is calculated. Then, the excitation search is performed according to different rates, and the pulse position and amplitude parameters are obtained, and after packing, the encoded data stream in units of frames is formed.
2 voice system structure and hardware schematic
The original analog voice is first converted to a digital signal by analog-to-digital conversion, then input to the DSP through the serial port, and then the speech compression algorithm. The G.723.1 standard calculation complexity and large data storage problems make the real-time implementation of the speech codec scheme have many difficulties. In order to ensure the real-time processing of the algorithm, the system uses DSP as the main control chip to implement the codec algorithm. The overall hardware structure of the voice system is shown in Figure 2.
3 voice system hardware design
The core components of this baseband system use CPLD and DSP. The DSP is responsible for the digital processing of the baseband, and the CPLD is used for the control of peripheral devices. Combining CPLD and DSP technology, on the one hand, the flexibility of DSP software control, on the other hand, the high speed, high integration and programmability of CPLD hardware.
This system selects TMS320C5509A (referred to as C5509A) to be responsible for the G.723.1 standard algorithm and subsequent baseband digitization processing (channel coding, interleaving, scrambling, CRC, baseband modulation and demodulation). The chip is one of the TMS320C55X series DSPs. The structure of the C55X series can be found in the reference [1].
CPLD is mainly used to expand the external address space of the DSP, realize address decoding, timing control, and provide the required logic and timing control signals to the DSP. This system selects EPM7128 in Altera's MAX7000 series, and its interface circuit with DSP is shown in Figure 3(a), in which the synchronization signals of FSX and FSR frame synchronization signal terminals are the same. The original analog voice signal must be digitized before the voice compression codec algorithm can be performed in the DSP. The system selects the low-cost, low-power general-purpose analog front end AD7311L from Analog Devices, and its interface circuit with DSP is shown in Figure 3(b). Because of G. The algorithm of 723.1 is more complicated, and requires a large amount of storage space during processing. This design uses 4Mb & TImes; 16 SDRAM, the chip is MT48LCM16, and is mapped to the C5509A CEO space through the EMIF interface. Its interface circuit with DSP is shown in Figure 3(c).
4 voice system software design
The overall software flow is shown in Figure 4. When the DSP is in the transmitting state, it receives the digitized voice data from the AD7311L through the MCBSP1, calls the voice compression encoding program, compiles the output data of one frame, and then proceeds to the subsequent related baseband processing. When the DSP is in the receiving state, it receives the data from the subsequent baseband processing, and calls the speech decoding program; the decoded speech data is sent to the AD7311L through the MCBSP1 for each frame of data, and finally restored to the original speech. The following mainly introduces the initialization module and the voice codec module.
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