8-bit unsigned multiplication operation HDL design example

Addition, subtraction, multiplication and division are the basis of the calculations, and they are also the key compulsory courses in the primary school classroom. Although the multiplication and division operation is still a piece of cake for us today, letting the computer do a lot of work is not enough. But if you really want to explore how the computer completes the division and calculation, there are some learning and skills, not the human brain. 9 flashed past 81, and although the computer may get results faster than people, it doesn't know how many orders of magnitude, but it still needs a process. It is possible that the internal computing principles and mechanisms of the different CPUs are slightly different. We can't completely clarify these computing methods. In this routine, we honestly complete two 8-bit unsigned numbers by shifting and accumulating. Multiplication operation. Here we will give an example of our operation principle, such as 8-bit unsigned number 189 and 25 multiplication. Because computers only know 0 and 1, the basis of all operations is 0 and 1, so our operations must also be based on binary. Therefore, we must first complete the conversion of the mechanism. The binary number corresponding to the multiplier 189 is 10111101, and the binary number corresponding to the multiplicand 25 is 00011001. According to our most commonly used decimal multiplication, we can get the binary multiplication shown in Figure 1. In this operation, we judge whether the value is 1 or 0 from the lowest bit to the highest bit of the multiplicand. If it is 1, it accumulates the multiplier, otherwise it does not accumulate (that is, takes 0), and the accumulated multiplier is needed. According to the current multiplicand bit, the corresponding shift is needed. If the bit 3 of the multiplicand is 1, the multiplier is shifted to the left by 3 times (that is, amplified by 8 times) as the accumulated number. According to this principle, the 8-bit unsigned multiplication we want to design is also the final result by multiplying the multiplicand by the bitwise judgment and then accumulating the left shift.

Figure 1 Binary multiplication In our 8-bit unsigned multiplication, some basic interface signals and their functions are: 8-bit unsigned numbers ain and bin are the two multipliers that need to be operated; the output is 16 The bit unsigned number yout indicates that the enable signal is the operation enable signal; the ready signal is the operation completion flag. The user first assigns a value to ain and bin, then starts the operation after the enable signal is pulled high. The output is output after about 8 clock cycles. The high output of the ready signal indicates that the operation result is valid. If the enable signal is pulled low by the user, then ready. The signal is then pulled low, indicating that an operation is completed. Then the user can assign a new operation value to ain and bin, and then raise the enable signal to continue a new operation. Verilog reference example module mux( clk,rst_n, enable,ain,bin,yout,read );input clk;input rst_n;input enable; (1)input[7:0] ain; (2)input[7:0] (3)output reg[15:0] yout; (4)output reg ready; (5)reg[4:0] i; (6) always@(posedge clk) if(!rst_n) begin ready <= 1'b0; yout <= 16'h0000; i <= 4'd0; end else if(enable) begin if(i < 4'd8) i <= i+1'b1; else ; if(i < 4' D7) begin (7) ready <= 1'b0; if(ain[i]) yout <= (yout+{1'b0,bin,7'd0})>>1; (8) else yout <= yout> >1; (9) end else if(i == 4'd7) begin (10) if(ain[i]) yout <= yout+{1'b0,bin,7'd0}; (11) else ; (12) ready <= 1'b1; (13) end else ready <= 1'b0; end else begin i <= 4'd0; yout <= 16'h0000; endendmodule

The operation enable signal. 0 means no operation; 1 means multiplication of the currently input ain and bin.

8-bit unsigned number, which will be multiplied by bin.

8-bit unsigned number, which will be multiplied by ain.

A 16-bit unsigned number used to store the result of multiplying two 8-bit unsigned numbers.

The multiplication operation completes the flag bit. After the current operation is completed, the output is high, and if the enable signal is pulled low, the signal is also pulled low.

Shift counter, when enable=1, each clock cycle i will increment until i=8 stops. When i=0~7, the shift accumulation calculation is performed correspondingly.

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