Why do small pitch LED displays require a splicer?
A key application of the splicer is to output multiple DVI signals and splicing multiple display screens in a matrix to make it a logical display area.
For the LED display , we can define the display area driven by one LED controller as a separate LED display. The current LED controller uses DVI/HDMI as the signal input interface to support the maximum input resolution. 1920 × 1200 @ 60Hz, the maximum bandwidth is 165MHz, the maximum physical resolution of the LED display driven is 1920 × 1200.
As the display area of ​​LED small-pitch products is getting larger and larger, dozens of square meters of projects are not uncommon. The physical resolution of LED displays often exceeds 1920×1200, that is, each piece of ultra-large-scale LED display is made up of several The LED controller is composed of several independent display areas. For the application of the splicer, only a number of DVI output interfaces are needed corresponding to the number of LED controllers, and the entire LED screen can be spliced ​​and displayed.
Small pitch LED image stitching processor requirements
(1) Synchronization of the output of the certificate to avoid the phenomenon that the spliced ​​picture is not synchronized;
(2) Optimize the image processing algorithm to keep the scaled image high definition;
(3) Custom output resolution, which should deal with the irregular physical resolution of LED display.
Splicing processing technology applied to small-pitch LED display
Key technologies for small pitch LED display splicers:
(1) Signal output synchronization
The multi-channel DVI signal output of the splicer must have the synchronization problem of the signal. The unsynchronized signal is output to the LED display screen, and the tearing phenomenon occurs at the splicing place, which is especially noticeable when playing a high-speed moving image. How to ensure the synchronization of the output of the signal becomes the key to measuring the success or failure of a splicing system.
(2) graphics processing algorithm
We know that the point-to-point image display is the best. After the reduced image, if only ordinary graphics processing technology or general-purpose FPGA graphics processing algorithm is used, the edges of the image will be jagged, and even pixels will be missing. The brightness will also drop. High-end image processing chips or FPGA systems that utilize complex graphics processing algorithms will maximize the display of reduced images. Therefore, a good graphics processing algorithm is a key technology for splicers used in small-pitch LED displays.
(3) Non-standard resolution output
The small-pitch LED display is made up of a matrix of display units of the same specification. Each display unit size and physical resolution are fixed, but the entire large screen is not a standard physical resolution. For example, the resolution of the display unit is 128×96, which can only be spelled as 1920×1152, but it cannot spell 1920×1080. In a very large-scale splicing system, the LED display area driven by each LED controller may not be the standard resolution. At this time, the output of the splicer with non-standard resolution is critical, which can help us find the right one quickly. The splicing method, so as to allocate resources reasonably, effectively saves the number of LED controllers and transmission equipment used.
Type of splicer for small pitch LED displays
At present, splicers can be divided into four categories, namely embedded pure hardware architecture, PCI-E bus architecture, distributed network architecture, and hybrid architecture.
(1) Embedded pure hardware architecture
The whole structure is usually designed with “backplane + signal acquisition board + main control board + signal output boardâ€. The signal acquisition board performs signal processing such as video capture, zoom, overlay, format conversion, etc., and will pass through the backplane bus. The processed signal is transmitted to the FPGA signal processing system of the main control board, and the functions of the main control FPGA configuration, the communication with the host PC, and the data exchange between the systems are realized through the embedded ARM system, and the signal is output to the display terminal through the signal output board. .
The structure of the pure hardware architecture splicer is relatively simple, and it is not easy to cause system failure; the acquisition board and the output board can be hot-swapped and easy to replace; the multi-channel and multi-format signal acquisition and processing can be realized; the back-board switching technology and the output board The card unified clock technology ensures the synchronization of multiple signal outputs; the resolution of each DVI output signal can be customized to meet the splicing characteristics of the LED display.
Many features make pure hardware architecture quickly become one of the mainstream products in today's splicer field. However, due to the adoption of FPGA as the core image processing unit, the advantages and disadvantages of the algorithm determine the processing effect of a splicer, especially the image scaling algorithm, how to optimize to achieve a clearer display effect, has become a judgment An important indicator of the value of pure hardware splicer products.
(2) PCI-E bus architecture
Usually the bus architecture splicer uses PCI Express technology, and the available data bandwidth is up to hundreds of Gbps. The host is equipped with a high-performance CPU and large-capacity memory, and can be pre-installed with different operating systems (such as 64-bit Windows 7) depending on the application domain, and can directly run various applications. The splicer is equipped with multiple high-performance graphics output cards, each with an ultra-high internal bandwidth and video memory, and all output images are synchronized to eliminate image tearing between display units. It also has multiple input cards, supports multiple signal formats, and is capable of image processing of input signals.
The PCI-E bus architecture splicer is a high-performance computer. All components are selected from the most advanced and mature technologies of major hardware manufacturers. For example, the CPU can be Intel, and the graphics card can be used by NVIDIA. All high-tech in the computer field can also be quickly integrated. This makes the PCI-E bus architecture splicer have incomparable advantages in terms of computing speed, image processing, and operation mode.
The PCI-E bus architecture splicer threshold is very low, for a simple application, an industrial computer, plus a professional multi-channel output graphics card can be achieved.
On the other hand, how to solve the problem of system stability, how to design an intuitive and powerful control software, how to solve various problems of data transmission under high bus bandwidth, etc., all need a strong R & D team and a solid financial foundation, The accumulation of experience is required. That is to say, the high-end PCI-E bus architecture splicer not only needs to meet the most basic applications such as signal acquisition, processing, and splicing, but also needs more investment in terms of system stability, software usability, etc. The splicer is designed to meet a variety of demanding applications.
However, it should be noted that the bus architecture splicer mostly uses the Windows operating system. Once it is attacked by a virus, it may cause the system to crash and stop displaying. Moreover, due to the use of custom graphics cards, the resolution of each output channel generally needs to comply with the VESA (Video Electronics Standards Association) standard, can not define non-standard resolution output, nor can define the different resolution of each channel.
(3) Distributed network architecture
The distributed network architecture splicer usually adopts a node-type hardware structure, and each input and output node is separately separated, and the data is exchanged and transmitted through the twisted pair to access the central switch.
The core is an advanced video codec technology that processes and encodes the collected DVI, VGA, YPbPr, CVBS, 3G-SDI signals through various signal input nodes, and encodes them through a dedicated network communication protocol. The subsequent video is transmitted to the output node for decoding via the central switch, and converted to a DVI digital signal for output to the display terminal.
Synchronization of the output nodes becomes the key to the application of the system. One method is to directly send synchronization codes through the network to realize synchronous output of multiple output nodes. However, due to the existence of the network error rate, after this mode of operation for a period of time, the output will be out of sync. Another method is to physically connect multiple output nodes through the SYNC interface, select one output node as the host, and actively send synchronization codes to other output nodes, so that all output nodes receive synchronization signals at the same time, realizing true frame synchronization. Output, ensuring that the displayed image is complete and there are no tears in the screen splicing.
At present, the application of distributed network architecture splicing system is more and more, due to its distributed characteristics, it is convenient for integrated wiring in the whole building and centralized management of multiple display terminals in different areas. With the help of advanced visualization software, we can provide users with personalized, visual and integrated services.
However, limited by bandwidth and codec technology, distributed network architecture does not currently support dual-link DVI digital and HDMI signal access. At the same time, since the encoding, processing, decoding, and signal synchronization output all require frame buffering, there is a gap in the real-time performance of data compared with other splicing technologies. In addition, when the number of points to be displayed exceeds 1920×1200 resolution (two or more signal input nodes are required), the resynchronization output of the multi-channel sync source input signal cannot be guaranteed.
(4) Hybrid architecture
A hybrid architecture generally refers to a splicer or splicing system in which two or more of the above three splicing techniques are combined.
For example, PCI+ hardware backplane bus architecture splicer, its system control and image processing are implemented independently. The PCI bus is responsible for system control and runs the operating system in the background; the hardware backplane bus is responsible for video image processing, and the system allows simultaneous processing of a large number of high-resolution input signals while still maintaining real-time operational performance at full frame rate and Optimal image quality while ensuring synchronism of the output signal. For important emergency places, it can be ensured that the black screen will never be black. Even if the operating system responsible for the PCI bus is faulty or virus infected, the dedicated backplane graphics processing bus can ensure that the external video image is displayed at any time.
Through the hybrid architecture, it is possible to integrate applications, complement each other, and greatly increase the stability of the system. This is also the development direction of the future splicing technology, with a broader application space.
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