The IEEE 1149.1 boundary-scan test standard (commonly referred to as JTAG, 1149.1, or "dot 1") is an industry-standard method for performing characterization tests on complex ICs and boards. Most complex electronic systems use this or that The IEEE 1149.1 (JTAG) standard is used in this way. In order to better understand this method, this article will explore how JTAG is used in system development and design in different eras, and promote the design to a new generation by leveraging the experience or input of JTAG access in the past.
Most complex electronic systems use the IEEE 1149.1 (JTAG) standard in one way or another. If the system is using a complex FPGA or CPLD, it is almost certain that the hardware is set up via the JTAG port. If the system uses simulation tools to debug hardware or software, then the simulation tool is most likely to talk to the microprocessor through the JTAG port. Moreover, if a ball grid array (BGA) packaged IC is used in the system, JTAG is also the most efficient way to test the connection between the BGA device and the underlying printed circuit board.
Both the IC and the board supporting the EEE 1149.1 boundary scan test standard have a 4-wire serial bus that supports JTAG testing (the 5th line is an optional reset line) - TDI (test data input), TDO (test data output) , TMS (test mode selection) and TCK (test clock). The bus primarily supports structural testing of solder joints, board vias, shorts, and open connections. In addition, many CPLD and FPGA manufacturers also use JTAG as their standard method of system programming and configuration. Not only does JTAG support structural (interconnect) testing, it is now a standard method for configuration, programming, and mixed-signal testing at the system level.
However, most of the design teams in the new design are more inclined to use JTAG in one step, but in a more controllable way to fully utilize the JTAG interface. Some team rules (discipline) make extensive use of the JTAG interface, while others only use a very limited part of it. But each rule adjusts JTAG according to its own needs. Under the joint action of various rules, several generations of different JTAG applications have been developed. Each generation of JTAG applications has its own characteristics and some enhancements.
Figure 1: Second-generation JTAG application: Simplify access to multiple JTAG chains with JTAG multi-drop multiplexers.
Due to the wide variety of JTAG access requirements, the development team must adopt a cross-rule JTAG access strategy to maximize JTAG access. This strategy is necessary to implement a standard approach that can be reused and the next generation of products can be built on top of it. To better understand this approach, we will explore how JTAG is used in system development and design in different eras, with the goal of driving design to a new generation by leveraging past experience or input on JTAG access.
Various stages of the JTAG applicationIn the first phase of the JTAG application, only some of the features and functions of the board were used, and the finishing and standardization of the method was done very little.
This is the easiest way to invest almost any software tool, usually with a free tool from an IC vendor. JTAG at this stage usually does not have or has very limited diagnostic capabilities, and there is no software available to generate test or programmed vectors. The JTAG access at this time is only used to configure the CPLD or program the flash during production. A slightly more complicated board can also be used for testing.
However, this is not the lowest cost method. Because each rule has the potential to use a separate JTAG header for its own needs, multiple JTAG connectors are used on a single board, increasing cost and board space. Moreover, each rule may develop their own "homemade" software tools and hardware to enable interaction with JTAG features that are redundant with respect to other disciplines. Therefore, the products developed by this method are affected by the custom development and it is difficult to transfer to a new generation of products. If used in production, this method also adds cost because it requires multiple insertions.
Many development teams have been tied to this generation of JTAG applications. Ultimately, as system complexity continues to increase, to maintain product competitiveness, a JTAG access strategy is required.
Second generation JTAG applicationIn the second generation of JTAG applications, different development team rules govern the use of JTAG functionality in new board designs. This phase of JTAG applications requires a degree of investment in ATPG (Automated Test Program Generation) software tools (which have robust diagnostic capabilities) for managing the development and delivery of programming and test vectors. Vendors of such ATPG tools provide support and consulting services from simple vector generation for each task, as well as full-featured multi-tasking (mulTI-seat) software support for production.
A strategic IC device, the JTAG multiplexer, is added to each board to remove multiple 1149.1 connectors on the board and manage multiple JTAG paths. This JTAG multiplexed device typically occupies less board space than a JTAG connector, but simplifies component isolation and simplifies the organization of the scan path required to improve access efficiency.
For example, developers may want to isolate FPGAs from different vendors in different scan chains to simplify the process of accessing JTAG using the tools provided by each vendor. In addition, we may also want to place the microprocessor in a separate scan chain to maximize the speed of the microprocessor when debugging software debugging software or writing programs in flash memory. ATPG vendors provide excellent support for these devices, so software support is usually simple and provides a turnkey solution.
Figure 2: Third Generation J: Extend the JTAG bus to connect multiple boards across the backplane.
Today, our second-generation design has only a single JTAG access point. In this basic configuration, all simulation, configuration, and 1149.1 tests for the entire board can be inserted in one test station at one test station (test staTIon). It is implemented with a PC-based system.
A new JTAG bus application has emerged at this stage - JTAG access is available throughout the life of the product. For example, the entire board-level vector image can be archived to reprogram or debug the board when field service is required. The same access function can also be used for field FPGA firmware upgrades or for diagnosing problems in a FRU (Field Replaceable Unit). Devices that return to the manufacturer for failure analysis can also isolate the problem using the same set of vector diagrams (and manufacturers or development test stations).
If there is any downside to this generation of JTAG applications, it is that the development team usually has a single board mentality. This is a common mentality, and the responsibility of the design team is limited to the board and its interface. However, if it is not possible to evolve to third-generation JTAG, this JTAG application has a bottleneck that limits the ability to implement multiple boards using JTAG.
Third generation JTAG applicationThe next generation of JTAG access is achieved when the JTAG features can be used at the multi-board system level on a backplane. In this environment, the card-level JTAG function can still be implemented separately, and the functions between the boards can also be utilized. This generation of JTAG applications not only promoted the cooperation of different design teams on the single board, but also promoted the cooperation between different board design teams under the whole system. If a JTAG multiplexer is used in the previous generation of JTAG applications, this multiplexer supports multi-tribute (mulTI-drop) access. With an addressing scheme, the serial JTAG bus can be used in multi-drop configurations to provide support for multiple boards. Once JTAG can access multiple boards on a backplane, system-level configuration or programming can be achieved (for example, JTAG can access multiple boards in parallel).
If the driver/receiver pair can allow JTAG-accessible full-speed BIST (built-in self-test), can also test backplane interconnects between boards, or can verify high-speed LVDS serial links between boards, then The integrity of the backplane interconnection between the boards can be tested or the high speed LVDS serial connection between the boards can be verified. Or these high speed interconnects are capacitively coupled and supported by the driver/receiver for IEEE 1149.6 testing.
All of these JTAG features are available using the same device as the second generation - a PC-based JTAG station. This PC-based JTAG station is used as a JTAG master device and is connected to the JTAG connector on the backplane via a separate set of lines. This master device is responsible for driving the test vector and managing the device access JTAG function on the entire backplane.
One of the most interesting new features added to the third-generation JTAG application allows access to the entire system through this sideband JTAG channel while the system is running. This feature enables many system-level features such as online “health†condition monitoring, failure prediction, fault detection, fault insertion (for failover testing or redundancy testing), and diagnostics.
Fourth generation JTAG applicationWhen the transmission and management of test vectors occur inside the system, the application of JTAG reaches the highest level, namely the fourth generation. The fourth-generation JTAG application uses an onboard JTAG host controller to drive the backplane JTAG bus. At the same time, the on-board memory is used to store the test vectors and a microprocessor is used to drive the JTAG master controller. The multi-board system-level main controller can be located on a separate board, or a main controller can be placed on each board to enhance control performance.
In the fourth generation, all previous generations of JTAG applications can be implemented remotely, including programming, configuration, interconnect testing, and diagnostics, dramatically reducing the cost of field service and support. When it is necessary to upgrade the firmware of a field system, the new configuration file is directly downloaded to the JTAG main controller, and then sent to the target device by the JTAG main controller through the backplane JTAG bus. Of course, PC-based JTAG access stations can still be used as long as the main controller is disabled during production, which further enhances flexibility and provides the most access options in all integrations.
JTAG access can be initiated externally or internally, or by some system event, such as system power up or power reset.
Summary of this articleTo date, the biggest obstacle to JTAG application and integration is how to make people aware of the need for a strategy based on multiple development rules and to convince managers that such a strategy can bring economic benefits. Once this step is taken and ATPG support and JTAG multiplexed devices are used, it is easier to incrementally evaluate or implement new JTAG functions step by step or from generation to generation. Moreover, if the development team can based on previous experience with JTAG, the JTAG bus can be better utilized.
Increasing the complexity of the JTAG structure does not necessarily become a burden on the system. On the contrary, JTAG can be fully utilized as a widely supported, system-level test, programming, configuration, and health monitoring of modern complex electronic systems. The full value of the industry standard approach.
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