Due to inherent advantages such as low temperature deposition, film purity, and excellent coverage, ALD (Atomic Layer Deposition) technology has been used in semiconductor fabrication since the beginning of the 21st century. The high-k dielectric deposition of DRAM capacitors is the first to adopt this technology, but recently ALD has also been developed more and more widely in other semiconductor process fields.
ALD deposition of high-k gate dielectrics and metal gates has become standard for advanced logic wafers, and this technology is being used for double- and quad-lithographic patterns (SDDP, SDQP) for deposition interval definitions to promote tradition The use of immersion lithography to define the minimum feature size for high density logic and memory design. The industry is shifting to three-dimensional structures, which in turn leads to the need for ALD for key film layers.
In the past, although several PVD and CVD steps could be used in planar components, the transition to FinFET components would require a full range of ALD solutions from the standpoint of gate stacking. The FinFET size and control of critical component parameters for the gate last processing requires a full ALD layer for the 14nm process. Interestingly, the use of FinFETs slows down the need for performance boosting for dielectric EOT scaling, and can adjust the gate dielectric thickness at slower speeds.
The thickness of cerium oxide (HfO2) has been reduced to less than 15 angstroms for the latest generation of components, and further physical scaling will result in incomplete layer formation; for the scaling of cerium oxide, it seems that 10 to 12 angstroms have reached the limit. However, with additional elements that increase the gate stack k value and can use thicker layers of the solid, the material can be expected to continue to be used in more generations to reduce tunnel leakage current.
FinFETs are an effective way to solve some of the key integration challenges in planar structures, especially controlling short channel effects and controlling random doping perturbations using lightly doped or undoped channels. However, for advanced process nodes, the fin width has been below the lithography limit and an ALD layer is required for the spacer defined double lithography pattern definition (SDDP) fin structure.
Wire edge roughness and CD圴 uniformity play a key role in fin definition, and fin variation can cause disturbances in the critical voltage between components or wafers. The etching of the fins must be effectively controlled to minimize crystal damage while minimizing fin height variations. Since the shadowing effect of the adjacent fins affects the ion implantation technique, uniform doping of the fins can be challenging. Plasma doping has similar problems.
Tapering the fins can solve the aforementioned problems and solve the concerns of overlying gate dielectric and metal deposition, but the next generation still needs to utilize high doping, uniformity, solid doping of ALD layers, and the like. A novel approach to continuously scale the fins.
In the FinFET and multi-gate elements, the sides and upper portions of Fin are active channel regions. Therefore, the high-k gate dielectric and metal gate must be deposited on the fin with minimal thickness and physical property variations. Variations can cause critical voltage variations and performance variations between the transistors, or reduce the current carrying capacity of the fins. In addition, the gate contact metal must provide a void-free fill to the gate cavity. Layer-by-layer ALD deposition quickly became the only technology to solve these problems.
In the standard planar replacement gate technology, the metal gate stack has been composed of a combination of ALD, PVD, and CVD metal layers. ALD is used for the criTIcal barrier and work funcTIon setting layers, while conventional PVD and CVD are used to deposit pure metals to low resistivity gate contacts.
With the advent of three-dimensional structures such as FinFETs, omni-directional ALD solutions are critical for dielectrics, barriers, and work funcTIon set-up layers and gate contacts. The maximum thermal budget continues to be low, and theoretically the metal deposition must be carried out at temperatures below 500 °C. The thermal ALD of pure metals is challenging in this temperature range, and most of the base materials that form pure metals at this temperature are unstable and will mix impurities into the metal during deposition.
However, the use of plasma enhanced ALD (PEALD) is highly advantageous, so this technique enables low temperature deposition of pure metals in a manner that minimizes impurities. Both direct and remote plasma can be used to deposit pure metal, but there are some concerns with the use of plasma near the gate region. The industry continues to evaluate different low temperature metal base materials to provide a solution for all temperatures by depositing pure metals by ALD.
The combination of 3D architecture and lower thermal budget will require CVD and PVD migration to ALD for specific critical thin film deposition applications. In the field of conventional PVD and CVD technology, we have observed a strong focus on ALD replacement. In the near future, ALD can be fully expected to expand to MEOL and BEOL applications. The development of ALD base metals is critical, especially in metal deposition spaces, for films that deliver characteristics that match the PVD/CVD baseline performance.
In addition to ensuring that the ALD base material has sufficient reactivity, the stability of the base metal and the vapor pressure are critical. If ALD largely replaces traditional PVD and CVD technologies, the future development of ALD base metals needs to be closely coordinated between chemical suppliers, equipment manufacturers and component manufacturers to ensure that these films can be deposited in a renewable, production-assured manner.
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