Hardware multipliers are an integral part of modern computers and are based on adder structures.
The hardware multiplier is based on the adder structure, which is already an essential part of modern computers. [1] The multiplier model is based on the "shift and add" algorithm. In this algorithm, each bit in the multiplier produces a local product. The first local product is generated by the LSB of the multiplier, the second product is generated by the second bit of the multiplier, and so on. If the corresponding multiplier bit is 1, then the local product is the value of the multiplicand. If the corresponding multiplier bit is 0, the local product is all 0. Each local product moves one bit to the left.
Multipliers can be represented in a more general way. Each input, local product number, and result are given a logical name (eg, A1, A2, B1, B2), and these names are used as signal names in the schematic. Comparing the signal names in the multiplication example of the schematic, the behavior of the multiplication circuit can be found.
In a multiplier circuit, each bit in the multiplier is summed with each bit of the multiplicand, and its corresponding product bit is generated. These local products are fed into an array of full adders (half-adders may also be used if appropriate), while adders are left-shifted and represent multiplication results. The resulting product terms are added in the CLA circuit. Note that some full-adder circuits will bring the signal to the carry input (used to replace the carry of adjacent bits). This is an application of a full adder circuit; the full adder adds any three bits at its input.
As the multiplier and the number of multiplicand bits increase, the adder bit tree in the multiplier circuit also increases accordingly. By studying the characteristics of CLA circuits, it is also possible to develop faster addition arrays in multipliers.
Circuit configuration
In theory, two binary N-bit operands are multiplied and the total width of the product is 2N, so a shift register and adder with a width of 2N are needed. However, during the actual execution, the width of each partial product and the effective width of shift addition are N bits. From the perspective of resource utilization, only the N-bit width adder is needed; The principle of shift and add first, two N-bit operands require 2N clock cycles to complete the entire operation, in this case consider the shift and add the two operation steps combined, from the speed can be N clocks Completed in cycle.
Based on the above analysis, an 8-bit-shift-add-type hardware multiplier should include four components, 16-bit latches, 8-bit shift registers, 8-bit multipliers, and 8-bit adders. The specific circuit structure is shown in Figure 1.
The latches act as latches to latch partial sums.
The shift register has a shift function. When the load signal is valid, the multiplier is loaded into the 8-bit right register. With the arrival of the rising edge of the clock, the multiplier starts shifting from the low position.
The multiplier function is similar to a special AND gate. There are two input ports, one for inputting 8-bit parallel operands (multiplicand) and the other for inputting serial operands shifted out by shift register under clock signal control, and these two operands Perform the AND operation.
The adder is used to add the sum of the 8-bit partial product obtained under this clock pulse control and the previous one clock pulse latched to the upper 8 bits of the latch.
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